Barrier enhancement process for copper interconnects

ABSTRACT

A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co—W—P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10 Å to 100 Å and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from U.S. Provisional Application Ser.No. 60/298,138, filed Jul. 25, 2001.

BACKGROUND OF THE INVENTION

This invention relates to an electrochemical deposition process fordepositing a thin film enhancement layer onto an existing ultra thinbarrier layer to repair defects and enhance the barrier properties ofthe barrier layer. The deposited thin film enhancement layer serves as abarrier layer and as a seed layer for subsequent copper platingprocesses.

Metallization patterns are needed to interconnect numerous devices toform integrated circuits. For high performance ultra large scaleintegration (ULSI) chips, six or more metallization layers are commonlyused. The number of layers is expected to increase as the industry worksto decrease device dimensions and pack more devices onto integratedcircuit chips.

Integrated circuit chip performance is limited by the signal propagationdelay of the interconnections, also known as the “RC” delay. In order toimprove circuit speed, it is important to reduce both the R (theresistance) and the C (the capacitance) associated with theinterconnections. Recently, copper metallization has been introduced toreplace aluminum metallization in integrated circuit fabrication becausecopper has both a lower resistivity and a higher current carryingcapacity than aluminum.

Copper metallization requires different processing than aluminummetallization. Instead of metal deposition followed by patterning asused in forming aluminum interconnects, copper interconnects usually areformed using a damascene process. In a damascene process, the conductorpattern is first etched into the dielectric material. Then, the etchedpatterns are filled with copper. Excess copper then is removed from overthe field using a chemical mechanical polishing (“CMP”) step. A via-holeis used to connect different metallization layers formed in theintegrated circuit chip. When the conductor line pattern and via-holepattern are filled and polished separately, the process is generallyreferred to as a “single damascene” process. When both the conductorline and the via-hole pattern are filled at the same time, the processis generally referred to as a “dual damascene” process.

In the known damascene process, a barrier layer and then a seed layerare deposited over the patterned dielectric layer surface before copperis introduced. The barrier layer is needed to prevent the copper fromdiffusing into the device region. When in contact with silicon, copperspoils the silicon device operation. Usually, thin refractory metals ormetal nitrides are selected for the barrier layer. Representativebarrier layer materials include tantalum, tantalum nitride, tungsten,tungsten nitride, titanium and titanium nitride. The seed layer isneeded to provide the conductivity for the electrochemical depositionreaction and to provide nucleation sites for the subsequent copperelectroplating. Usually, a thin copper layer is deposited over thebarrier layer to serve as the seed layer.

One of the most important requirements for the damascene process forcopper is to have the deposited copper perfectly fill the smallgeometries of etched lines or trenches and holes with high aspect ratios(calculated as depth divided by width). Electroplating processes aregenerally used to deposit copper because such processes have better gapfilling capability as compared to physical vapor deposition (“PVD”) orchemical vapor deposition (“CVD”). Because electrochemical copperdeposition processes can deposit more copper inside small trenches thanoutside the trenches, they are frequently called “super-filling.”

The PVD techniques include, for example, various evaporation andsputtering techniques, such as DC and/or RF plasma sputtering, biassputtering, magnetron sputtering, ion plating, or ionized metal plasmasputtering. PVD processes generally produce non-conformal deposition dueto their anisotropic and directional nature. The CVD techniques include,for example, thermal CVD, plasma enhanced CVD, low pressure CVD, highpressure CVD, and metal-organo CVD. CVD processes most frequentlyproduce conformal deposition with substantially uniform thickness overthe entire surface, including over the field and the bottom and sidewallsurfaces of the openings.

Currently, the barrier and seed layers are deposited primarily by PVDprocesses, such as sputtering and ionized sputtering. Frequently, thebarrier and seed layers are deposited sequentially in two differentvacuum chambers without breaking vacuum to avoid surface contamination.The critical factor in such deposition processes is the film thicknessinside the etched patterns, particularly on the sidewall and bottom ofetched lines or trenches and via holes. The PVD processes commonly formthinner film layers in these etched patterns than over the flat fieldregion of the dielectric material. The step coverage of these layers hasbeen problematic. The films must be continuous and defect free. A voidor defect in the barrier layer will compromise the integrity of thedevice. A void or defect in the seed layer will lead to a void or defectin the plated copper film.

To improve step coverage, CVD processes have been tried for depositingthe barrier and seed layers. The CVD processes have not yielded betterresults than the PVD processes, and CVD processes are more expensive.Copper seed layers deposited by CVD processes usually have pooradhesion, higher impurities and poor crystal orientation, leading toproblems when additional copper is electrochemically deposited over suchseed layers. Sometimes PVD is used in conjunction with CVD, such that aseparate copper seed layer is deposited by PVD processing over a copperseed layer deposited by CVD, further adding to the expense for CVDprocessing. Accordingly, PVD processing for barrier and seed layers forcopper interconnects has remained preferred despite noted difficultieswith step coverage.

Improvements to PVD deposition technology may not suffice to solveproblems with film coverage for the barrier layers and seed layersdeposited by PVD. As device dimensions continue to decrease, in thefuture the barrier film layer on the trench sidewall will need to beless than 10 nanometers. Combined technologies may be required to meetthe more rigorous requirements.

U.S. Pat. No. 6,136,707 teaches a method of combining a first copperseed layer formed by CVD with a second copper seed layer formed by PVD.U.S. Pat. No. 6,197,181 discloses a method of combining a first copperseed layer electrolytically deposited from an alkaline plating solutionwith a second copper seed layer formed by PVD. Both of these patentsthus require additional processing steps to achieve better PVD copperseed layer adhesion. However, the methods disclosed in these patents donot solve the problems caused by either a defective barrier layer or apoor interface between the barrier layer and the copper seed layer.

Accordingly, the industry seeks better methods for electrochemicallydepositing copper into high aspect ratio holes and trenches.

SUMMARY OF THE INVENTION

The invention comprises processes and apparatus for applying a metal toa microelectronic workpiece where the microelectronic workpiece includesa surface in which are disposed one or more micro-recessed structures.Most commonly, the microelectronic workpiece is a semiconductor wafer,such as a silicon or gallium arsenide semiconductor wafer. Preferably,the metal is copper applied to form metallization layers in trenches orholes or vias or other structures in the semiconductor wafer using adamascene or dual damascene process.

In the process according to the invention, the steps comprise:

-   -   (a) forming a barrier layer on the surface of the        microelectronic workpiece, including on the walls of the        micro-recessed structures;    -   (b) forming an enhancement layer over the barrier layer, wherein        said enhancement layer is comprised of a metal alloy; and    -   (c) electroplating a metal onto the enhancement layer so as to        fill the micro-recessed structure.

Preferably, the enhancement layer is formed to a thickness of 100 Å orless, most preferably from 10 Å to 100 Å, using an electrochemicaldeposition process, such as an electroless or an electroplating process.Alternatively, the enhancement layer may be formed using a CVD or PVDprocess.

In one embodiment, the enhancement layer is formed from a copper alloy,such as Cu—Al, Cu—Mg and/or Cu—Zn. In another embodiment, theenhancement layer is formed from a binary alloy composition, such asCo—P, or a tertiary alloy composition, such as Co—W—P.

The enhancement layer conformally covers the barrier layer, even wherethe barrier layer has seams, discontinuities or grain boundary defects.For a silicon semiconductor wafer, the barrier layer may be titanium,titanium nitride, or other known barrier layer materials. Theenhancement layer is conductive sufficient to permit deposition of ametal, preferably copper, thereon. Thereafter, excess metal is removedfrom the field surface, such as by chemical mechanical polishing. Thedeposited metal remains within the microelectronic structure forming thedesired interconnect or metallization layer.

In a further embodiment, the process steps comprise:

-   -   (a) forming a barrier layer on the surface of the        microelectronic workpiece, including on the walls of the        micro-recessed structures;    -   (b) forming an enhancement layer of a metal alloy over the        barrier layer;    -   (c) forming a seed layer over the enhancement layer; and    -   (d) electroplating a metal onto the enhancement layer so as to        fill the micro-recessed structure.

In this alternate embodiment, the seed layer may comprise a furtherlayer of a metal alloy or may comprise a layer of the metal intended tobe deposited in the microelectronic structure. Thus, the seed layer maybe a copper alloy, a binary alloy such as Co—P, or a tertiary alloy suchas Co—W—P. The seed layer is formed with a thickness preferably from 50Å to 500 Å.

The damascene processes may be carried out in a manufacturing lineincluding a plurality of apparatus for the manufacture ofmicroelectronic circuits or components, where one or more apparatus ofthe plurality of apparatus are used to apply interconnect metallizationin a damascene process to a surface of a microelectronic workpiece usedto form the microelectronic circuits or components. The microelectronicworkpiece preferably is a silicon or gallium arsenide semiconductorwafer into which has been formed holes or trenches or vias suited formetallization to form microelectronic circuits or components. In suchcase, the one or more apparatus comprise:

means for applying a barrier layer to a surface of the microelectronicworkpiece using a first deposition process, wherein the barrier layer isgenerally unsuitable for bulk electrochemical deposition of theinterconnect metallization;

means for applying an enhancement layer over the barrier layer using asecond deposition process, wherein the enhancement layer formed from analloy composition that is generally suitable for subsequentelectrochemical application of a metal to a predetermined thicknessrepresenting a bulk portion of the interconnect metallization; and

means for electrochemical application of a metal over the enhancementlayer.

Preferably, the means for applying the enhancement layer is equipmentfor electrochemical deposition, such as equipment for electroless orelectroplating processing. Alternatively, the means for applying theenhancement layer may be equipment for CVD or PVD processing. The meansfor applying the enhancement layer is capable of applying theenhancement layer conformally over the barrier layer to a thickness of100 Å or less, preferably from 10 Å to 100 Å thick. The enhancementlayer preferably is formed from a metal alloy, such as a copper alloylike Cu—Al, Cu—Mg and/or Cu—Zn, a binary alloy such as Co—P, or atertiary alloy such as Co—W—P, or possibly even from mixtures of suchalloys.

The means for electrochemical application of a metal over theenhancement layer is capable of applying copper as the metal in thedamascene process. Once the copper is introduced into the metallizationlayers or microelectronic structures, a means is provided for removing aportion of the copper metal from the field surface of themicroelectronic workpiece. Preferably, the means for removing a portionof the copper metal comprises chemical mechanical polishing equipment.

The apparatus may include a first chamber for applying the barrier layerand a second chamber for applying the enhancement layer. In addition,the optional additional seed layer and the copper metallization layermay be deposited onto the workpiece while the workpiece is in the secondchamber used to apply the enhancement layer. Thus, electrochemicaldeposition of the enhancement layer, the optional seed layer, and thecopper metal may be carried out in a single chamber in the apparatus.

DESCRIPTION OF THE FIGURES

The invention will be more fully understood by referring to the detailedspecification and claims taken in connection with the followingdrawings.

FIG. 1A is a cross-sectional view illustrating a silicon semiconductorwafer that has been etched to form a dielectric pattern trench;

FIG. 1B is a cross-sectional view illustrating the silicon semiconductorwafer with a trench wherein a thin barrier layer, such as tantalum ortantalum nitride, is shown as deposited uniformly over the surface;

FIG. 2 is a cross-sectional view of a silicon semiconductor wafer with atrench that has been coated with a thin barrier layer, and illustratingsurface defects most commonly formed in the thin barrier layer;

FIG. 2A is an enlarged cross-sectional view of the coated siliconsemiconductor wafer trench of FIG. 2;

FIG. 3 is a cross-sectional view of the silicon semiconductor wafer witha trench that has been coated first with a thin barrier layer, and thenwith a barrier enhancement layer according to the invention;

FIG. 4 is a cross-sectional view of the silicon semiconductor wafer ofFIG. 3, wherein the trench has been filled with copper using anelectrochemical deposition method;

FIG. 5 is a cross-sectional view of the silicon semiconductor wafer ofFIG. 4 after the surface has been polished to remove excess copper,leaving a completed damascened conductor pattern;

FIG. 6 is a cross-sectional view of an alternate embodiment wherein thesilicon semiconductor wafer has a completed damascened conductorpattern, and wherein a copper seed layer has been deposited over thebarrier enhancement layer before the trench was filled with copper; and

FIG. 7 is a graph of the deposition rate of Co—W—P alloy barrierenhancement film over a barrier layer at 75° C. in angstroms versus timein minutes.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring first to FIG. 1A, a silicon dielectric material 10, such asSiO₂, comprises a semiconductor wafer shown in enlarged partialcross-sectional view. The dielectric material 10 has a trench 12 formedtherein.

The surface of the dielectric material 10 is coated with a thin barrierlayer 14, preferably using a PVD process although a CVD process may alsobe used. The barrier layer generally may be a thin refractory metal ormetal nitride. Representative barrier layer materials include tantalum,tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride,tungsten silicon nitride, titanium, titanium nitride and titaniumsilicon nitride, and other tertiary nitrides.

As shown in FIG. 1A, the barrier layer 14 is formed as a continuouslayer or film without discontinuities or surface defects. This is theideal surface coverage for such a barrier layer. The barrier layerthickness is generally from 100 Å to 500 Å over the field and flatbottom surfaces within the trench, and depending upon the aspect ratioand opening size of the trench, 100 Å or less over the trench sidewall.For very small openings with large depths, the deposited film on thesidewall can be too thin, resulting in discontinuities and surfacedefects.

Referring next to FIGS. 2 and 2A, the barrier layer 16 formed over thedielectric material 10 is shown to have surface coverage defects withinthe trench 12. As illustrated in FIG. 2, the barrier layer 16 has notsmoothly covered the trench sidewall and flat bottom surface. Seams 18are left in the bottom corners where the barrier layer has not coveredthe dielectric material. Discontinuities 20 are breaks in the coveragealong the sidewalls. Grain boundaries 22 represent surface defects thatinhibit proper adhesion of a subsequent copper seed layer to be formedover the barrier layer in the known damascene process.

Most of the failures in the barrier layer relate to copper diffusion atthe grain boundaries because grain boundary diffusion is much fasterthan the diffusion through the bulk. It has been proposed to “stuff” thegrain boundaries to improve the barrier properties of the barrier layerwith grain boundary defects. For example, TiN barrier layers are usuallyannealed in an oxygen atmosphere to “stuff” the oxygen at the grainboundaries. Another method to reduce the diffusion at the grainboundaries is to add other materials to the original barrier metal toform alloys. The added material usually concentrates at the grainboundaries (also called segregation). Alloy composition can be adjustedto satisfy different requirements. For example, copper alloys, such asCu—Sn, Cu—Zn, Cu—Mg or Cu—Al can be used as diffusion barriers forcopper. The added metal in the alloy usually concentrates on the grainboundary surface or free surface and prevents the copper atoms frommoving. Cu—Sn and Cu—Zn are known to slow the corrosion of Cu in air bypreventing oxygen diffusion. Recently, Cu—Al has been studied as adiffusion barrier for copper because Al tends to segregate out at thegrain boundaries and at the surface.

One of the most difficult issues in depositing a seed layer over thebarrier layer is getting good adhesion between the original barrierlayer and the seed layer deposited thereon. Plated copper adheres poorlyto the barrier layer surface. That is why the seed enhancement layerdescribed in U.S. Pat. No. 6,197,181 was not directly deposited on thebarrier layer, but was deposited onto a PVD deposited copper seed layer.A CVD copper seed layer directly deposited onto the barrier layer alsohas poor adhesion, and a PVD copper seed layer is often used to improvethe adhesion of the CVD copper seed layer.

According to the invention, as shown in FIG. 3, a barrier enhancementlayer 24 is deposited conformally over the barrier layer 16, usingeither a CVD process, a PVD process or an electrochemical process. Anelectrochemical process or a CVD process are preferred. Anelectrochemical deposition process, such as electroless andelectroplating processes, are most preferred. The barrier enhancementlayer is from 10 Å to 100 Å thick, and covers the defects, such as theseams 18, the discontinuities 20, and the grain boundaries 22 present inthe barrier layer 16. The barrier enhancement layer has good stepcoverage.

The barrier enhancement layer 24 is intended both to enhance theperformance of the diffusion barrier layer and to serve as a seed layerfor subsequent copper plating processing. Thus, depositing the barrierenhancement layer can eliminate the need for a separate copper seedlayer.

The barrier enhancement layer is formed from a conductive metal thatwill adhere to the barrier layer and will also permit subsequent copperplating. Preferably, the barrier enhancement layer is formed from abinary or tertiary metal alloy material selected from one of thefollowing: cobalt-phosphorous (Co—P) or cobalt-tungsten-phosphorous(Co—W—P); or is formed from a copper alloy, such as Cu—Al, Cu—Mg, Cu—Znand/or Cu—Sn, or possibly mixtures of such alloys.

Preferably, the alloy material deposited as the barrier enhancementlayer is Co—W—P. Electrochemical deposition processes for Co—W—P aredescribed in detail in U.S. Pat. No. 5,695,810, which description isincorporated herein by reference. Typical deposition temperatures forthis alloy range from room temperature to 90° C. However, at 90° C., theloss of aqueous electrolyte by evaporation may be excessive, such that alower temperature, such as 75° C. is preferred. The thickness of thedeposited Co—W—P layer can be controlled by controlling the depositiontime and temperature for a given deposition chemistry. Co—W—P alloymaterial deposits over a TiN barrier layer at a rate of about 100 Å to200 Å per minute at 75° C. in an electrochemical deposition process asgraphically illustrated in FIG. 6.

The electrochemical deposition processes are preferred for depositingthe barrier enhancement layer. Such processes are compatible with thestandard copper plating process and equipment already in use in copperinterconnect fabrication. The new electrochemical deposition process forthe barrier enhancement layer therefore can readily be integrated withexisting plating tools by installing a new process chamber in theexisting system. A suitable integrated tool configuration is shown inFIG. 12 in U.S. Pat. No. 6,017,437. The integrated tool configurationreduces tooling costs and permits a simple wafer processing flowsequence. After the barrier enhancement layer is deposited, the wafercan be transferred directly to the copper plating module to complete theplating process without leaving the plating tool.

After the barrier enhancement layer 24 is applied over the barrier layer16, the etched pattern is filled with electroplated copper as shown inFIG. 4. Thereafter, the field surface is polished, preferably by achemical mechanical polishing (“CMP”) step, to remove the excess copper.A completed damascened conductor pattern after the CMP is completed isshown in FIG. 5.

In an alternate embodiment, two separate layers may be deposited ontothe barrier layer. As shown in FIG. 6, the enlarged cross-sectional viewof the dielectric wafer material 10 has a trench 12 formed therein. Abarrier layer 16 is deposited over flat bottom and sidewall surfaces ofthe trench, and has grain boundaries, seams and discontinuities thereinas noted in the prior embodiment. The barrier enhancement layer 24 isagain applied over the barrier layer 16. Thereafter, a seed layer 28 isformed over the barrier enhancement layer 24. The seed layer 28 may beformed as an alloy, such as used to form the barrier enhancement layer24 or may be copper metal. Although the seed layer may be deposited by aCVD, PVD or electrochemical deposition process, the electrochemicaldeposition processes are preferred. Moreover, it is more economical todeposit the barrier enhancement layer and the seed layer usingcompatible deposition processes, and preferably in the same tool.

EXAMPLES Example 1

A single barrier enhancement layer was deposited over a TiN barrierlayer. The TiN barrier layer was sputtered over a silicon dioxidedielectric material. The TiN barrier layer surface was then cleaned andrinsed. A thin electroless Co—W—P layer was then deposited over the TiNbarrier layer. The electrolyte used for deposition consisted of:

-   -   CoCl×6 H₂O 30 g/l    -   (NH₄)₂WO₄ 10 g/l    -   Na₃C₆H₅O₇×H₂O 80 g/l    -   NaH₂PO₂×H₂O 20 g/l    -   KOH to pH=9.5

The deposition temperature was 75° C. and deposition time was about oneminute. The deposited film (about 100 Å) had good diffusion propertiesand was used successfully as the seed layer for subsequent copperplating.

Example 2

A sputtered tantalum barrier layer was applied to the silicon dioxidedielectric substrate. Because direct deposition of Co—W—P onto tantalumis known to have marginal adhesion, a thin layer (about 100 Å) of cobaltwas sputtered onto the tantalum surface. Then, a layer of Co—W—P wasdeposited by electroless deposition onto the sputtered Co surface at 75°C. for about one minute. The combined film (approximately 200 Å)resulted in satisfactory adhesion. Copper was then directlyelectroplated onto the Co—W—P layer. In this example, the Co layer wasthe barrier enhancement layer and the Co—W—P was the seed layer forcopper plating.

This example illustrates that according to the second embodiment of theinvention: (1) two different layers may be used—a barrier enhancementlayer and a seed layer; and (2) different deposition techniques wereused for depositing the barrier enhancement layer and the seed layer.

The invention has been illustrated by detailed description and examplesof the preferred embodiments. Various changes in form and detail will bewithin the skill of persons skilled in the art. Therefore, the inventionmust be measured by the claims and not by the description of theexamples or the preferred embodiments.

1-61. (canceled)
 62. A process for applying a metal to a microelectronicwork-piece, the microelectronic work-piece including a surface in whichare disposed one or more micro-recessed structures, the processcomprising: (a) forming a barrier layer on the surface of themicroelectronic work-piece, including on the walls of the micro-recessedstructures; (b) forming a barrier enhancement layer over the barrierlayer, wherein said enhancement layer comprises a metal alloy selectedfrom the group consisting of Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P andCo—W—P; and (c) electroplating a metal onto the barrier enhancementlayer so as to fill the micro-recessed structure.
 63. The process ofclaim 62, wherein the enhancement layer is formed using anelectrochemical deposition process.
 64. The process of claim 63, whereinthe electrochemical deposition process is selected from the groupconsisting of electroless and electroplating processes.
 65. The processof claim 62, wherein the enhancement layer is formed using a CVDprocess.
 66. The process of claim 62, wherein the enhancement layer isformed using a PVD process.
 67. The process of claim 62, wherein theenhancement layer is formed with a thickness of 100 Å or less.
 68. Theprocess of claim 62, wherein the enhancement layer is formed with athickness in the range of from 10 Å to 100 Å thick.
 69. The process ofclaim 62, wherein the barrier layer so formed has seams, discontinuitiesor grain boundary defects, and wherein the enhancement layer conformallycovers the barrier layer.
 70. The process of claim 62, wherein the alloyis Co—P.
 71. The process of claim 62, wherein the alloy is Co—W—P. 72.The process of claim 62, wherein the metal electroplated onto theenhancement layer is copper.
 73. The process of claim 62, furthercomprising: (d) removing a portion of the metal from the surface of themicroelectronic work-piece.
 74. The process of claim 73, wherein theremoving is by chemical mechanical polishing.
 75. The process of claim62, wherein the microelectronic work-piece is a silicon or galliumarsenide semiconductor wafer.
 76. A process for applying a metal to amicroelectronic work-piece, the microelectronic work-piece including asurface in which are disposed one or more micro-recessed structures, theprocess comprising: (a) forming a barrier layer on the surface of themicroelectronic work-piece, including on the walls of the micro-recessedstructures; (b) forming a barrier enhancement layer of a metal alloyover the barrier layer, wherein said metal alloy is selected from thegroup consisting of Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P and Co—W—P; (c)forming a seed layer over the enhancement layer; and (d) electroplatinga metal onto the seed layer so as to fill the micro-recessed structure.77. The process of claim 76, wherein the enhancement layer is formedusing an electrochemical deposition process.
 78. The process of claim77, wherein the electrochemical deposition process is selected from thegroup consisting of electroless and electroplating processes.
 79. Theprocess of claim 76, wherein the enhancement layer is formed using a CVDprocess.
 80. The process of claim 76, wherein the enhancement layer isformed using a PVD process.
 81. The process of claim 76, wherein theenhancement layer is formed with a thickness of 100 Å or less.
 82. Theprocess of claim 76, wherein the enhancement layer is formed with athickness in the range of from 10 Å to 100 Å thick.
 83. The process ofclaim 76, wherein the barrier layer so formed has seams, discontinuitiesor grain boundary defects, and wherein the enhancement layer conformallycovers the barrier layer.
 84. The process of claim 76, wherein the alloyis Co—P.
 85. The process of claim 76, wherein the alloy is Co—W—P. 86.The process of claim 76, wherein the metal electroplated onto theenhancement layer is copper.
 87. The process of claim 76, furthercomprising: (e) removing a portion of the metal from the surface of themicroelectronic work-piece.
 88. The process of claim 87, wherein theremoving is by chemical mechanical polishing.
 89. The process of claim76, wherein the microelectronic work-piece is a silicon or galliumarsenide semiconductor wafer.